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NUS6160MN Low Profile Overvoltage Protection IC with Integrated MOSFET
This device represents a new level of safety and integration by combining an overvoltage protection circuit (OVP) with a dual 20 V P-channel power MOSFET. The OVP is specifically designed to protect sensitive electronic circuitry from overvoltage transients and power supply faults. During such events, the IC quickly disconnects the input supply from the load, thus protecting it. The integration of the additional transistor and power MOSFET reduces layout space and promotes better charging performance. The IC is optimized for applications that use an external AC-DC adapter or a car accessory charger to power a portable product or recharge its internal batteries.
Features http://onsemi.com MARKING DIAGRAM
1 QFN22 CASE 485AT NUS 6160 ALYWG G
* * * * * * * * * * * *
Overvoltage Turn-Off Time of Less Than 1.5 ms Undervoltage Lockout Protection; 3.0 V, Nominal High Accuracy Undervoltage Threshold of 5.0% -20 V Integrated P-Channel Power MOSFET Low RDS(on) = 64 mW @ -4.5 V Compact 3.0 x 4.0 mm QFN Package Maximum Solder Reflow Temperature @ 260C This is a Pb-Free Device Provide Battery Protection Integrated Solution Offers Cost and Space Savings Integrated Solution Improves System Reliability Optimized for Commercial PMUs from Top Suppliers
NUS6160 = Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
ORDERING INFORMATION
Device NUS6160MNTWG Package QFN22 (Pb-Free) Shipping 3000 / Tape & Reel
Benefits
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
Applications
* Portable Computers and PDAs * Cell Phones and Handheld Products * Digital Cameras
(c) Semiconductor Components Industries, LLC, 2008
December, 2008 - Rev. 0
Publication Order Number: NUS6160MN/D
NUS6160MN
N/C N/C GND In En 18 17 N/C
22
Out
1
N/C
N/C
N/C
Gate1
Flag
Drain1
Gate2
Drain1
FETSW Drain1 6
FETREG Drain2 12
Drain2
Drain1
N/C
7 Source2 Drain2 Source1 Drain1
11 Drain2 8 3 FETSW 4, 5, 6, 7
(Top View)
Figure 1. Pinout
Vbat
15 FLAG 20 Wall Adaptor IN
1
ChargeSW
OUT
EN NUS6160 18 19
GND FETREG 9, 11, 13 Battery
10 14 ChargeREG
Figure 2. Typical Charging Solution http://onsemi.com
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NUS6160MN
MAXIMUM RATINGS (TJ = 25C, unless otherwise stated)
Rating VIN to Ground OUT, EN, FLAG Pins Voltage to Ground Maximum Current from VIN to VOUT (PMOS) Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, Steady State Pulsed Drain Current, tp = 10 ms Source Current Operating Ambient Temperature Storage Temperature Operating Junction Temperature Thermal Resistance (Note 1) 1 in2 (645 mm2) (All devices fully enhanced) OVP FET FETSW FETREG 1 in2 (645 mm2) (OVP and FETSW fully enhanced, 1 V drop across FETREG) OVP FET FETSW FETREG 0.25 in2 (161 mm2) (All devices fully enhanced) OVP FET FETSW FETREG 0.25 in2 (161 mm2) (OVP and FETSW fully enhanced, 1 V drop across FETREG) OVP FET FETSW FETREG ESD Performance (Human Body Model) Pins 1, 15, 18, 19, 20 Lead Temperature for Soldering Purposes (1/8" from case for 10 s) Symbol VIN VOUT, VEN, VFLAG Imax VDSS VGS ID IDM IS TA TSTG TJ qJA 68 42 46 43 39 80 79 53 56 53 49 92 - TL 2.5 260 kV C -40 -55 -8.0 Min -0.3 -0.3 Max 21 7.0 600 -20 8.0 -2.0 -4.0 -1.1 85 150 150 Unit V V mA V V A A A C C C C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. 1 oz. copper, double sided board. Thermal impedance requires total for DT calculations. See example in thermal description.
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NUS6160MN
PIN DESCRIPTION
Pin 1 3 4, 5, 6, 7 8 9, 11, 13 10 12 14 15 2, 16, 17, 21, 22 Name Out Gate FETSW Drain FETSW Source FETSW Drain FETREG Source FETREG N/C Gate FETREG FLAG N/C Description This pin is the output of the internal OVP chip. It must be connected to the source of the upper FET (Pin 8). This pin is the gate of the upper FET which is normally used for a switch in series with the battery. It is controlled by the PMU. These pins are the drain of the upper FET. For the lowest on resistance connect all pins together. This set of pins must be connected to the source of the lower (regulator) FET, Pin 10. This pin is the source of the upper FET and must be connected to the output pin of the internal OVP chip (Pin 1). These pins are the drain of the lower FET which is normally used for the regulation function. It connects to the positive terminal of the battery. This pin is the source of the lower FET and must be connected to the drain pins of the upper FET. This pin has no internal connections and is isolated from all internal circuitry within the chip. This pin is the gate of the lower FET which is normally used for the regulation function in series with the battery. It is controlled by the PMU. The fault flag is an open drain output and therefore requires a pullup resistor. The FLAG pin will be driven low when the input voltage exceeds the OVLO trip level. These pins are connected to the ground of the analog chip. This is a medium impedance connection and should not be used for the ground signal. These pins should either be left floating or connected to ground, but not any other potential. If these pins are connected to ground, the ground pin (19) must still be used. The ENABLE pin must be held low for normal operation. When this pin is tied high the unit will be shut down. The state of the enable pin has no impact on the FAULT pin. This is the ground reference pin for the internal OVP chip. This pin is the input to the internal OVP chip and connects to the wall, or car adaptor.
18 19 20
EN Gnd In
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NUS6160MN
OVP ELECTRICAL CHARACTERISTICS
(Min/Max limits values (-40C < TA < +85C) and Vin = +5.0 V. Typical values are TA = +25C, unless otherwise noted.) Characteristic Input Voltage Range Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis Overvoltage Lockout Threshold Overvoltage Lockout Hysteresis Vin versus Vout Dropout Supply Quiescent Current OVLO Supply Current Output Off State Current FLAG Output Low Voltage FLAG Leakage Current EN Voltage High EN Voltage Low EN Leakage Current TIMINGS Start Up Delay FLAG going up Delay Output Turn Off Time ton tstart toff From Vin > UVLO to Vout = 0.8xVin, See Fig 3 & 9 From Vin > UVLO to FLAG = 1.2 V, See Fig 3 & 10 From Vin > OVLO to Vout 0.3 V, See Fig 4 & 11 Vin increasing from normal operation to >OVLO at 1V/ms. No output capacitor. From Vin > OVLO to FLAG 0.4 V, See Fig 4 & 12 Vin increasing from normal operation to >OVLO at 1V/ms From EN 0.4 to 1.2V to Vout 0.3V, See Fig 5 & 13 Vin = 4.75 V. No output capacitor. 4.0 3.0 0.8 1.5 15 ms ms ms Symbol Vin UVLO UVLOhyst OVLO OVLOhyst Vdrop Idd Iddovlo Istd Volflag FLAGleak Vih Vol ENleak Vin = 5 V, I charge = 500 mA No Load, Vin = 5.25 V Vin = 8 V Vin = 5.25 V, EN = 1.2 V Vin > OVLO, Sink 1 mA on FLAG pin FLAG level = 5 V Vin from 3.3 V to 5.25 V Vin from 3.3 V to 5.25 V EN = 5.5 V or GND 170 1.2 0.4 5.0 Vin rises up OVLO threshold Vin falls down UVLO threshold Conditions Min 1.2 2.85 30 6.9 50 3.0 50 7.07 100 105 24 50 26 Typ Max 20 3.15 70 7.4 125 200 35 85 37 400 Unit V V mV V mV mV mA mA mA mV nA V V nA
Alert Delay
tstop
1.0
2.0
ms
Disable Time
tdis
2.0
ms
Thermal Shutdown Temperature Thermal Shutdown Hysteresis NOTE:
Tsd Tsdhyst
150 30
C C
Thermal Shutdown parameter has been fully characterized and guaranteed by design.
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NUS6160MN
MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted, all parameters apply to both FETSW and
FETREG) Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage Drain-to-Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current V(Br)DSS V(Br)DSS/TJ IDSS IGSS VGS(TH) VGS(TH)/TJ RDS(ON) gFS CISS COSS CRSS QG(TOT) QGS QGD td(ON) tr td(OFF) tf VSD tRR ta tb QRR VGS = 0 V, dIS/dt = 100 A/ms, IS = 1.0 A VGS = 0 V, IS = -1.1 A VGS = -4.5 V, VDD = -16 V, ID = -2.6 A, RG = 2.0 W VGS = -4.5 V, VDS = -16 V, ID = -2.6 A VGS = -4.5 V, ID = -1.0 A VGS = -4.5 V, ID = -0.6 A Forward Transconductance CHARGES, CAPACITANCES, AND GATE RESISTANCE Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-to-Source Charge Gate-to-Drain Charge SWITCHING CHARACTERISTICS (Note 3) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time DRAIN-SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge -0.8 20 15 5 0.01 mC -1.2 V ns 5.5 12 32 23 ns VGS = 0 V, f = 1.0 MHz, VDS = -16 V 750 100 45 7.6 1.3 2.6 8.6 nC pF VDS = -10 V, ID = -2.9 A VGS = 0 V VDS = -16 V TJ = 25C TJ = 85C VGS = 0 V, ID = -250 mA -20 -15 -1.0 -5.0 "100 nA V mV/C mA Symbol Test Condition Min Typ Max Unit
Gate-to-Source Leakage Current ON CHARACTERISTICS (Note 2) Gate Threshold Voltage Gate Threshold Temperature Coefficient Drain-to-Source On Resistance
VDS = 0 V, VGS = "8.0 V VGS = VDS, ID = -250 mA -0.45 2.7 64 62 7.0
-1.5
V mV/C
80 80
mW
S
2. Pulse test: pulse width 300 ms, duty cycle 2% 3. Switching characteristics are independent of operating junction temperatures
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NUS6160MN
Vin UVLO ton Vout tstart FLAG 1.2 V 0.8 Vin Figure 3. Start Up Sequence
Figure 4. Shutdown on Over Voltage Detection
EN
1.2 V tdis
EN
1.2 V OVLO
Vout Vin - RDS(on) x I FLAG
0.3 V
Vin
UVLO 3 ms
FLAG
Figure 5. Disable on EN = 1
Figure 6. FLAG Response with EN = 1
CONDITIONS IN OUT VIN > OVLO or VIN < UVLO
Voltage Detection
Figure 7.
CONDITIONS IN OUT UVLO < VIN < OVLO
Voltage Detection
Figure 8.
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NUS6160MN
TYPICAL OPERATING CHARACTERISTICS
Figure 9. Startup Vin = Ch1, Vout = Ch3
Figure 10. FLAG Going Up Delay Vout = Ch3, FLAG = Ch2
Figure 11. Output Turn Off Time Vin = Ch1, Vout = Ch2
Figure 12. Alert Delay Vout = Ch1, FLAG = Ch3
Figure 13. Disable Time EN = Ch1, Vout = Ch2, FLAG = Ch3
Figure 14. Thermal Shutdown Vin = Ch1, Vout = Ch2, FLAG = Ch3
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NUS6160MN
TYPICAL OPERATING CHARACTERISTICS
450 400 350 RDS(on) (mW) 300 250 200 150 100 50 0 -50 0 50 TEMPERATURE (C) 100 150 Vin = 5 V Vin = 3.6 V
Figure 15. Direct Output Short Circuit
180 160 140 120 100 80 60 40 20 0 1 3 5 7 9 11 13 15 -40C 25C 125C
Figure 16. RDS(on) vs. Temperature (Load = 500 mA)
IQ, SUPPLY QUIESCENT CURRENT (mA)
17
19
21
Vin, INPUT VOLTAGE (V)
Figure 17. Supply Quiescent Current vs. Vin
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NUS6160MN
TYPICAL PERFORMANCE CURVES (TJ = 25C unless otherwise noted)
10 -ID, DRAIN CURRENT (AMPS) 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 -1.8 V -1.6 V -1.4 V 7 8 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS = -10 V to -2.8 V TJ = 25C -ID, DRAIN CURRENT (AMPS) -2.4 V 9 8 7 6 5 4 3 2 1 0 0 25C 125C TJ = -55C 4
1 1.5 2 3 3.5 0.5 2.5 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 18. On-Region Characteristics
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 0.2 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2 3 4 5 -ID, DRAIN CURRENT (AMPS) 6 VGS = -4.5 V VGS = -2.5 V 1.5
Figure 19. Transfer Characteristics
VGS = -4.5 V 1.3 1.1 0.9 0.7 0.5 -50
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
Figure 20. On-Resistance vs. Drain Current and Gate Voltage
10000 VGS = 0 V -IDSS, LEAKAGE (nA) 1000 100 10 1 0.1 TJ = 125C TJ = 100C
Figure 21. On-Resistance Variation with Temperature
TJ = 25C 2 3 4 5 6 7 8
-VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 22. Drain-to-Source Leakage Current vs. Voltage
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NUS6160MN
TYPICAL PERFORMANCE CURVES (TJ = 25C unless otherwise noted)
1000 900 C, CAPACITANCE (pF) 800 700 600 500 400 300 200 100 0 0 2 Crss 4 6 8 10 12 14 16 Coss 18 20 Ciss 5 QT 4 3 Q1 2 1 0 Q2 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1.2 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
TJ = 25C
ID = -2.7 A TJ = 25C 0 1 4 2 3 5 6 Qg, TOTAL GATE CHARGE (nC) 7 8
-VGS -VDS
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 23. Capacitance Variation
1000
Figure 24. Gate-to-Source and Drain-to-Source Voltage vs. Total Gate Charge
5 -IS, SOURCE CURRENT (AMPS) 4 3 2 1 0 0.4 VGS = 0 V TJ = 25C
VDD = -10 V ID = -1.0 A VGS = -4.5 V
t, TIME (ns)
100
10
td(off) tf tr td(on)
1 1 10 RG, GATE RESISTANCE (OHMS) 100
0.5
0.6
0.7
0.8
0.9
1.0
1.1
-VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 25. Resistive Switching Time Variation vs. Gate Resistance
100 -I D, DRAIN CURRENT (AMPS)
Figure 26. Diode Forward Voltage vs. Current
10
10 ms 100 ms 1 ms 10 ms
1
0.1
VGS = -8 V SINGLE PULSE TC = 25C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT
dc
0.01 0.1
10 1 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
100
Figure 27. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com
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NUS6160MN
Operational Description
The NUS6160 provides overvoltage protection for positive voltages up to 20 V. A P-Channel FET protects the load connected on the Vout pin, against positive overvoltage conditions. The Output follows the VBUS level until OVLO threshold is reached.
Undervoltage Lockout (UVLO)
in the event of an overvoltage condition to protect the output from a positive overvoltage condition. The low Rds(on), during normal operation will minimize the voltage drop across the device. (See Figure 16).
ESD Tests
To ensure proper operation under all conditions, the device has a built-in undervoltage lock out (UVLO) circuit. As the input ramps from 0 V, the output remains disconnected from input until the Vin voltage is above 3.2 V nominal. The FLAG output is pulled to low as long as Vin does not reach the UVLO threshold. This circuit incorporates hysteresis on the UVLO pin to provide noise immunity to transient condition.
The NUS6160 meets the requirements of the IEC61000*4*2, level 4 (Input pin, 1 mF mounted on board). For the air discharge condition, Vin is protected up to $15 kV. In the contact condition, Vin is protected up to 8 kV ESD. Please refer to Figure 29 to see the IEC 61000-4-2 electrostatic discharge waveform.
Figure 29. IEC 61000-4-2 Curve Figure 28. Output Characteristic vs. Vin Overvoltage Lockout (OVLO) Thermal Impedance
To protect connected systems on Vout Pin from overvoltage, the device has a built-in overvoltage lock out (OVLO) circuit. During an overvoltage condition, the output remains disabled until the input voltage is reduced to below the OVLO hysteresis level. The FLAG output is tied to low until Vin is higher than OVLO. This circuit incorporates hysteresis on the OVLO pin to provide noise immunity from transient conditions.
FLAG Output
The NUS6160 provides a FLAG output, which alerts external systems that a fault has occurred. This pin goes low as soon as the OVLO threshold is exceeded. When Vin level recovers to its normal range the FLAG is set high. The FLAG Pin is an open drain output, thus a pullup resistor (typically 1 MW - Minimum 10 kW) must be provided to Vbattery.
EN Input
To enable normal operation, the EN pin shall be forced low or connected to ground. A high level on the pin disconnects the OUT Pin from IN Pin. EN does not override an OVLO or UVLO fault.
Internal PMOS FET
The NUS6160 includes an internal PMOS FET which connects the input to the output pin. This FET is turned off
Due to cross heating of the three dice in the package, the equivalent thetas are given for this device rather than the individual thetas. To calculate the junction temperatures of a single die, the total power must be used. For example, given the following parameters, the die temperatures will be as shown: Idc = 500 mA RDS(on) OVP = 305 mW RDS(on) FETsw = 72 mW FETreg has a 1.0 V Drop Board copper area = 161 mm2 Calculate the individual power dissipations: POVP = (0.50 A)2 x .305 W = 0.076 W PSW = (0.50 A)2 x .072 W = 0.018 W PREG = 0.50 A x 1.0 V = 0.50 W PTOT = 0.076 + 0.018 + 0.50 = 0.594 W From the Maximum ratings table for thetas, 161 mm2 and 1 V drop across FETREG: OVP FET 53C/W FETSW 49C/W FETREG 92C/W The die temperature rises above ambient are: TOVP = 53C/W x 0.594 W = 32C TSW = 49C/W x 0.594 W = 29C TREG = 92C/W x 0.594 W = 55C
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NUS6160MN
PACKAGE DIMENSIONS
QFN22, 3x4, 0.5P CASE 485AT-01 ISSUE B
D A B L1 DETAIL A
OPTIONAL CONSTRUCTIONS
L
L
PIN 1 REFERENCE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PADS AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN NOM MAX A 0.80 0.90 1.00 A1 0.00 0.025 0.05 A3 0.20 REF b 0.20 0.25 0.30 D 3.00 BSC D2 1.45 1.50 1.55 D3 0.52 0.57 0.62 D4 1.02 1.07 1.12 E 4.00 BSC E2 1.05 1.10 1.15 E3 1.30 1.35 1.40 E4 1.40 1.45 1.50 e 0.50 BSC K 0.25 --- --- L 0.30 0.325 0.35 L1 --- --- 0.15 G 1.35 1.40 1.50 G1 0.95 1.05 1.15 G2 0.855 0.885 0.915
2X
0.15 C
2X
A1
DETAIL B
0.15 C 0.10 C
25X
TOP VIEW
DETAIL B
OPTIONAL CONSTRUCTIONS
A 0.08 C A3
SEATING PLANE
NOTE 4
SIDE VIEW G1 D3
7
A1
C
DETAIL A
D4
12
22X
L 0.50 PITCH
G
E3
E4
G
E2
22X 1
b 0.10 C A B 0.05 C
NOTE 3
16X
K
18
e G2 D2 BOTTOM VIEW
22X
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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CCC EEE EEE
1 1.47 4.30 1.47 0.52
22X
EE EE EE
EEE EEE EEE EEE
E
EXPOSED Cu MOLD CMPD
A3
SOLDERING FOOTPRINT*
3.30 1.55 0.925
PACKAGE OUTLINE
1.21
1.47 1.58
0.39 0.30
1.14
DIMENSIONS: MILLIMETERS
NUS6160MN/D

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